FPGA (Field-Programmable Gate Array) is a semi-custom integrated circuit. The user can program a FPGA into a desired digital integrated circuit chip by programming. FPGA is optimal for digital signal interfaces due to the flexibility.
LVDS (Low Voltage Differential Signaling) interface based data communication is widely used in devices including image sensors for its high data transmission rate, low noise and low power consumption. Two clock output channels are provided for LVDS: a positive and a negative differential clock signal ends.
When processing data with an FPGA and LVDS, one LVDS link can occupy one PLL and one pair of dedicated clock pins of FPGA. FIG. 1 shows a connection according to existing technologies by which only one image sensor can be connected to an FPGA which has only one pair of dedicated clock pins. If two LVDS differential clock signals are input respectively, the FPGA can perform a fusion calculation to obtain a clock signal for sampling the input data signal. The data signal can be sampled based on the clock signal.
The PLL and dedicated clock pins are limited resources of a FPGA. The prior connection of a link having dual clock signals with clock pins of an FPGA limits a number of sensors, which have dual clock signals such as cameras, to be connected to a FPGA.